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2015 Project Titles in VLSI

S.NO	2015 VLSI	DOMAIN	YEAR
1	A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT	VLSI	2015
2	A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications	FIR FILTER	2015
3	A High-Speed FPGA Implementation of an RSD-Based ECC Processor	VLSI	2015
4	Aging-Aware Reliable Multiplier Design with Adaptive Hold Logic Multilevel Conditional Probability	VLSI	2015
5	An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability	VLSI	2015
6	An Efficient Constant Multiplier Architecture Based on Vertical- Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis	FIR FILTER	2015
7	An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multi-standard DUC	FIR FILTER	2015
8	Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design	VLSI	2015
9	Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging	VLSI	2015
10	Exact and Approximate Algorithms for the Filter Design Optimization Problem	FIR FILTER	2015
11	Fault Tolerant Parallel Filters Based on Error Correction Codes	FIR FILTER	2015
12	Graph-Based Transistor Network Generation Method for Supergate Design	VLSI	2015
13	High - Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations	FIR FILTER	2015
14	Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs	VLSI	2015
15	Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System	FIR FILTER	2015
16	Optimal Factoring of FIR Filters	FIR FILTER	2015
17	Recursive Approach to the Design of a Parallel Self-Timed Adder	VLSI	2015
18	Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block	VLSI	2015
19	Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations	VLSI	2015
20	Aging-Aware Reliable Multiplier Design with Adaptive Hold Logic	VLSI	2015
21	Algorithm and Architecture Design of the H.265/HEVC Intra Encoder	VLSI	2015
22	All Digital Energy Sensing for Minimum Energy Tracking	VLSI	2015
23	An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders	VLSI	2015
24	An Efficient Constant Multiplier Architecture Based on Vertical- Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis	FIR Filter	2015
25	An Efficient List Decoder Architecture for Polar Codes	VLSI	2015
26	Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator	VLSI	2015
27	Architecture for Monitoring SET Propagation in 16-bit Sklansky Adder	VLSI	2015
28	Area-Efficient 3-Input Decimal Adders Using Simplified Carry and Sum Vectors	VLSI	2015
29	Comparative Performance Analysis of the Dielectrically Modulated Full-Gate and Short-Gate Tunnel FET-Based Biosensors	VLSI	2015
30	Design and Analysis of Inexact Floating-Point Adders	VLSI	2015
31	Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating	VLSI	2015
32	Design of Efficient Content Addressable Memories in High- Performance FinFET Technology	VLSI	2015
33	Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging	VLSI	2015
34	Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA	VLSI	2015
35	Energy Consumption of VLSI Decoders	VLSI	2015
36	Exact and Approximate Algorithms for the Filter Design Optimization Problem	VLSI	2015
37	Fast Code Design for Overloaded Code-Division Multiplexing Systems	VLSI	2015
38	Fine-Grained Access Management in Reconfigurable Scan Networks	VLSI	2015
39	FPGA-Based Bit Error Rate Performance Measurement of Wireless Systems	VLSI	2015
40	Fully Pipelined Low-Cost and High-Quality Color Demosaicking VLSI Design for Real-Time Video Applications	VLSI	2015
41	Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications	VLSI	2015
42	Graph-Based Transistor Network Generation Method for Supergate Design	VLSI	2015
43	High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design	VLSI	2015
44	High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule	VLSI	2015
45	Implementation of Subthreshold Adiabatic Logic for Ultralow- Power Application	VLSI	2015
46	In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers	VLSI	2015
48	Integrating Lock-Free and Combining Techniques for a Practical and Scalable FIFO Queue	VLSI	2015
49	Learning Weighted Lower Linear Envelope Potentials in Binary Markov Random Fields	VLSI	2015
50	Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs	VLSI	2015
51	Long-Distance Measurement Applying Two High-Stability and Synchronous Wavelengths	VLSI	2015
52	Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication	VLSI	2015
53	MAC With Action-Dependent State Information at One Encoder	VLSI	2015
54	Minimum Parallel Binary Adders with NOR (NAND) Gates	VLSI	2015
55	Modified Wallace Tree Multiplier using Efficient Square Root Carry Select Adder	VLSI	2015
56	Modulation Classification of Single-Input Multiple-Output Signals Using Asynchronous Sensors	VLSI	2015
57	Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications	VLSI	2015
58	Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System	FIR Filter	2015
59	Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications	VLSI	2015
60	Obfuscating DSP Circuits via High-Level Transformations	VLSI	2015
61	One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes	VLSI	2015
62	Partially Parallel Encoder Architecture for Long Polar Codes	VLSI	2015
63	Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding	VLSI	2015
64	Range Unlimited Delay-Interleaving and –Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit	VLSI	2015
65	Recursive Approach to the Design of a Parallel Self-Timed Adder	VLSI	2015
66	Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations	VLSI	2015
67	Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI	VLSI	2015
68	Shift Register Design Using Two Bit Flip-Flop	VLSI	2015
69	Signal Design for Multiple Antenna Systems With Spatial Multiplexing and Noncoherent Reception	VLSI	2015
70	Synthesis of Genetic Clock with Combinational Biologic Circuits	VLSI	2015
71	Timing Error Tolerance in Small Core Designs for SoC Applications	VLSI	2015
72	Two-Step Optimization Approach for the Design of Multiplierless Linear-Phase FIR Filters	FIR Filter	2015
73	VLSI-Assisted Non-rigid Registration Using Modified Demons Algorithm	VLSI	2015